Incremental Compilation for Logic Emulation

Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic gates. While software support for translating new user designs from gate and RTL-level netlists to FPGA bitstreams has improved steadily, little work has been done in developing techniques to support the translation of incremental design changes at the netlist level to a set of replacement bitstreams for a small number of FPGAs in a multi-FPGA system. As system sizes and design compilation times increase, the need to support rapid, incremental compilation grows progressively important. In this paper we describe and analyze a set of incremental compilation steps, including incremental design partitioning and incremental inter-FPGA routing, for two specific classes of multi-FPGA emulation systems. These classes are defined by the techniques that emulation software systems use to determine inter-FPGA communication. In hard-wired emulation systems each logic signal traversing an FPGA boundary is dedicated to a physical inter-FPGA wire and this assignment remains static during the execution of the prototyped design. In contrast, for virtual-wired systems, inter-FPGA wires are multiplexed over time during design execution to support the communication of multiple logical signals using the same physical resources. Through experimentation we find that while incremental compilation techniques can be applied both to hard-wired and virtual-wired systems, a lack of available FPGA pin resources frequently limits their applicability in the hardwired case. In contrast, it is shown that incremental techniques can be seemlessly integrated into virtual-wired systems resulting in a valid implementation of a modified design and requiring the need to re-place and re-route only a small fraction of FPGAs in the target system.